Regviz

Freescale Semiconductor /MK70F15WS /SIM /CLKDIV2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIV2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MK61F15WS/SIM/CLKDIV2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (USBFSFRAC)USBFSFRAC 0USBFSDIV 0RESERVED 0 (USBHSFRAC)USBHSFRAC 0USBHSDIV 0RESERVED

Description

System Clock Divider Register 2

Fields

USBFSFRAC

USB FS clock divider fraction
USBFSDIV

USB FS clock divider divisor
RESERVED

no description available
USBHSFRAC

USB HS clock divider fraction
USBHSDIV

USB HS clock divider divisor
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data